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Ddr3 pcb layout rules

Ddr3 pcb layout rules

DDR
The first step is to determine the topology (only useful for multiple DDR chips)
 
In a word, DDR1 / 2 adopts star structure, DDR3 adopts chrysanthemum chain structure. The extension structure only affects the routing mode of address line, but does not affect the data line.

Star expansion means that the address line goes to the middle of two pieces of DDR, and then goes to the two pieces of DDR separately. Chrysanthemum chain is to "string up" the two pieces of DDR with the address line, just like a mutton kebab. Each DDR is a piece of meat on the mutton string. Ha ha, I'm joking.

The second step is to place the components
 
After determining the extension structure of DDR, the components can be placed. The following principles should be observed:
 
Principle 1, consider the extension structure, carefully check the location of the CPU address line, so that the address line is conducive to the corresponding extension structure
 
Principle 2: the matching resistance on the address line is close to the CPU
 
Principle 3: the matching resistance on the data line is close to DDR
 
Principle 4: place and rotate the DDR chip to make the DDR data cable as short as possible, that is, the data pin of DDR chip is close to the CPU
 
Principle 5: if there is a VTT termination resistor, place it as far as the address line can go. Generally speaking, DDR2 does not need VTT termination resistance, only a few CPUs need it; DDR3 all need VTT termination resistor.
 
Principle 6: the decoupling capacitance of DDR chip is placed near the corresponding pin of DDR chip
 
The third step is to set up the simulation model of series matching resistance
 
After placing the components, it is suggested to set up the simulation model of series matching resistance, which is beneficial to the subsequent setting of wiring rules.

The fourth step is to set the line width and line distance
 
1. The line width of DDR is closely related to impedance control, and it is often seen that many peers do impedance control. For pure digital circuit, it is completely possible to do single end impedance control for high-speed line; but for mixed circuit, including high-speed digital circuit and RF circuit, RF circuit is more important than digital circuit, so 50 ohm impedance control must be done for RF signal. At the same time, RF wiring cannot be too thin, otherwise it will cause large loss, so in mixed circuit, I often give up Abandon the impedance control of digital circuit. Up to now, the highest specification DDR is ddr2-800 among the hybrid circuit products designed by me. Without impedance control, everything works normally.
 
2. It is recommended that the power supply line of DDR should be more than 8mil. In Allegro, the physical parameters of a class of lines can be set. I like to establish the constraint condition of pwr-10mil and assign this constraint condition to all power supply networks.
 
3. In the part of line distance, two aspects are mainly considered: one is the line line spacing, which is suggested to adopt the 2W principle, that is, the line spacing is twice the line width, and 3W is difficult to meet; the other is the line shape spacing, which is also recommended to adopt the 2W principle. For line spacing, a constraint can also be established in Allegro to assign such constraints to all DDR routes (xnet).
 
4. Another rule that may be needed is regional rule. The default line width and line spacing in Allegro are 5MIL. When the CPU pins are relatively dense, such rules can not be met. Therefore, it is necessary to set the area rules that allow small spacing and small line width around the CPU or DDR chip.
 
Step five: route
 
There are a lot of things to pay attention to when routing. Here, only a little explanation is given here.
 
All wiring should be as short as possible
 
There must be no sharp angle in the wiring
 
Make as few holes as possible

Ensure that all wiring has a complete reference plane. The ground plane or the power plane can be used. For alternating signals, the ground and the power plane are equipotential
 
It is difficult to break the reference surface by vias, but it is difficult to do so in practice
 
After going through the address line and data, be sure to run all the power pins, grounding pins, decoupling capacitor power pins and grounding pins of DDR chips, otherwise it will be very troublesome to wind the same length in the back
 
The sixth step is to set the equal length rule
 
For data lines, the rules of DDR1 / 2 and DDR3 are consistent: each byte is equal to its own DQS and DQM, that is, dq0:7 and dqs0, DQM. Dq8:15 is equal to dqs1, dqm1, and so on.
 
In terms of address line length, special attention should be paid to DDR1 / 2 and DDR are very different.
 
For DDR1 / 2, it is necessary to set the distance from each address to the same DDR to keep the same length.
 
For DDR3, the same length of address line often needs vias to match. The specific rules are bound to vias and VTT termination resistance, as shown in the figure below. It can be seen that the distance from the CPU address line to the via hole is the same as that from the via hole to the VTT termination resistance.
 
In addition, many times, the length of address line is not strict, which I have not tried. In these products designed by me, the address line and data line are all set with 25mil equal length rule of relative propagation delay. The details of isometric rule setting will not be repeated here.
 
The seventh step, winding equal length
 
After completing the setting of the equal length rule, the last step is also the most workload step: winding equal length.
 
In this step, I think there is only one rule to pay attention to: try to use 3 times the line width, 45 degree angle winding equal length.
 
After winding the same length, it is better to lock the DDR related network to avoid misoperation.

At this point, the PCB design with DDR has been completed.

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