Digital devices are developing towards the direction of high speed, low consumption, small size and high anti-interference, which development trend puts forward many new requirements for the design of high frequency PCB. Based on years of experience in hardware design, the author summarizes some techniques of high frequency PCB wiring for your reference.
(1) High frequency PCB tend to have high integration and high wiring density. The use of multilayer boards is both necessary for wiring and an effective means to reduce interference.
(2) The less the lead bending between the pins of high-speed circuit devices, the better.
(3) The shorter the lead between the pins of high-frequency circuit devices, the better.
(4) The less alternating lead layers between the pins of high-frequency circuit devices, the better.
(5) In hf circuit wiring, attention should be paid to the "cross interference" introduced by the signal line running parallel at close distance. If parallel distribution cannot be avoided, a large area of "ground" can be arranged on the opposite side of the parallel signal line to greatly reduce interference.
(6) The method of grounding a particularly important signal line or a local unit, that is, drawing the outer contour of the selected object.
(7) The wiring of various signals cannot form a loop, and the ground wire cannot form a current loop.
(8) A high-frequency decoupling capacitor shall be set near each integrated circuit block.
(9) High frequency choke shall be used when connecting analog ground wire and digital ground wire to the common ground wire.
(10) Analog circuit and digital circuit should be arranged separately. After independent wiring, a single point should be connected to the power supply and ground to avoid mutual interference.
(11) Before the DSP, off-chip program memory and data memory are connected to the power supply, the filter capacitor should be added and made as close as possible to the chip power supply pin to filter out the power supply noise.
(12) Pieces of program memory and data memory should be placed close to DSP chip, and reasonable layout, make almost consistent data and address line length, especially when the system has many pieces of memory to consider the clock line to equidistant from each memory clock input or add separate programmable clock driver chip.