PCB Parasitic Capacitance Calculator | Trace & Layer Capacitance

🔍 Calculation Mode

Between PCB Traces (Coplanar) Between Power/Ground Planes

🧪 Dielectric Material (εr @ 1 MHz typical)

Permittivity affects capacitance linearly – higher εr = higher parasitic C.

📐 Trace-to-Trace Parameters (coplanar)

Length of parallel run (mm)

Copper thickness (e.g., 0.035mm for 1oz)

Edge-to-edge gap between traces

📌 Model: C = ε₀·εr·(L·t)/S. This simplified approximation assumes uniform field between sidewalls.

📐 Plane-to-Plane Parameters (parallel plate)

Length of overlapping region

Width of overlapping region

Prepreg/core thickness between planes

📌 Formula: C = ε₀·εr·(A)/d, where A = length × width.

📖 Engineering background: Parasitic capacitance can cause crosstalk, EMI, and signal integrity issues. The parallel-plate model is accurate for power planes; trace-to-trace is a first-order estimate (sidewall capacitance). For stripline/microstrip, add fringe effects.

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⚡ PCB Parasitic Capacitance Tool